The Future of the Microprocessor Business

Ivory Vandezande

Why don’t microprocessor makers simply start producing lower-performance chips? A few years ago, Intel Corp. (Santa Clara, Calif.) began doing just that with its Celeron microprocessor. The problem is that Celeron is a one-size-fits-all proposition. Its architecture isn’t more modular than that of the Pentium products it is displacing, and it cannot be customized nearly as much as emerging alternatives.

Interestingly, while the latest microprocessors offer higher processing rates than most users need, semiconductor fabrication facilities now offer circuit design teams more transistors than they need.



Paul Sakuma/AP Photo

Microprocessors hundreds of times as powerful as today’s should emerge from chip-making equipment using extreme ultraviolet radiation. Sandia National Laboratories unveiled such equipment a year ago [above].

Put another way, the rate at which engineers are capable of using transistors in new chip designs lags behind the rate at which manufacturing processes are making transistors available for use.

This so-called design gap has been widening for some time. In fact, the National Technology Roadmap for Semiconductors noted it five years ago, observing that while the number of transistors that could be put on a die was increasing at a rate of about 60 percent a year, the number of transistors that circuit designers could design into new interdependent circuits was going up at only 20 percent a year.

The fact that microprocessor designers are now “wasting” transistors is one indication that the industry is about to re-enact what happened in other technology-based industries, namely, the rise of customization. Keep in mind that in order to develop a modular product architecture with standardized interfaces among subsystems, it is necessary to waste some of the functionality that is theoretically possible. Modular designs by definition force performance compromises and a backing away from the bleeding edge.

Core customization

A form of customization has already taken hold in the lower tiers of the microprocessor industry. System-on-a-chip (SoC) products are modular designs constructed from reusable intellectual property (IP) blocks that perform specific functions [see “Crossroads for Mixed-Signal Chips,” IEEE Spectrum, March 2002, pp. 38-43]. IP blocks vary in size and complexity, ranging from simple functions such as an RS-232 serial port interface or a DRAM memory controller, to a complex subsystem, such as an entire 32- or 64-bit microprocessor. These IP blocks can be used within multiple designs within a company, or used in designs at different firms.

In the lower market tiers, several firms are bundling IP blocks into both soft cores (software-like descriptions of the IP blocks that can be synthesized into hardware designs) and hard cores, that is, pre-verified hardware designs. Such cores range from hundreds of thousands to a few million transistors, and their availability in the marketplace enables firms to focus less on new design and more on system integration. They can select and integrate microprocessor and other types of cores into SoC designs that are then manufactured as special-purpose components for a specific product.

Recently, a few companies have been pushing this trend toward component selection and integration even further, into microprocessor cores themselves. Using special design tools, engineers can specify such a microprocessor, and in some cases completely design one, in weeks rather than months.

Leading companies in this so-called customizable core movement include Tensilica, ARC Cores, Hewlett-Packard, and STMicroelectronics. They have a similar philosophy, but target different markets and application needs. The Tensilica Xtensa processor, for instance, offers customization within the framework of a simple microprocessor core. Customers can specify their own instruction set extension by accessing a Web site and using a high-level language, such as Verilog.

ARC Cores’ ARCtangent family targets the digital signal processor markets. Like Tensilica, it allows users to customize both processor features (bus widths, cache sizes, and so on) and instructions. Hewlett-Packard’s HP/ST Lx family is aimed at scalable multimedia acceleration using Very Long Instruction Word (VLIW) techniques. It lets customers choose the amount of instruction-level parallelism–in other words, how many functional units to include, and how many operations can be performed in parallel.

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